TY - DATA T1 - Data and code underlying the research of: Robust logic for STT based CIM PY - 2024/02/16 AU - Abhairaj Singh UR - DO - 10.4121/09195299-6318-4e2f-8542-2bd945a9688c.v1 KW - computation in memory KW - logic KW - sense amplifier KW - stt-mram N2 -

This work targets BNN-related applications. Given the inherent low sensing margins due to low TMR of STT devices, this work proposes an adaptive referencing mechanism to improve the sensing margin while performing logic operations in an STT-MRAM-based CIM. Reference signals are generated using multiple STT-MRAM devices and placed strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. The concept is demonstrated using an STT-MRAM model, which is calibrated using 1Mb characterized array at IMEC and is validated by deploying it in a BNN. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

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